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Article

Profile Guided Dataflow Transformation for FPGAs and CPUs

Citation
Stewart R, Bhowmik D, Wallace A & Michaelson G (2017) Profile Guided Dataflow Transformation for FPGAs and CPUs. Journal of Signal Processing Systems, 87 (1), pp. 3-20. https://doi.org/10.1007/s11265-015-1044-y

Abstract
This paper proposes a new high-level approach for optimising field programmable gate array (FPGA) designs. FPGA designs are commonly implemented in low-level hardware description languages (HDLs), which lack the abstractions necessary for identifying opportunities for significant performance improvements. Using a computer vision case study, we show that modelling computation with dataflow abstractions enables substantial restructuring of FPGA designs before lowering to the HDL level, and also improve CPU performance. Using the CPU transformations, runtime is reduced by 43 %. Using the FPGA transformations, clock frequency is increased from 67MHz to 110MHz. Our results outperform commercial low-level HDL optimisations, showcasing dataflow program abstraction as an amenable computation model for highly effective FPGA optimisation.

Keywords
dataflow; profiling; transformations; FPGA; CPU;

Journal
Journal of Signal Processing Systems: Volume 87, Issue 1

StatusPublished
Author(s)Stewart, Robert; Bhowmik, Deepayan; Wallace, Andrew; Michaelson, Greg
FundersEngineering and Physical Sciences Research Council
Publication date30/04/2017
Publication date online02/10/2015
Date accepted by journal14/09/2015
URLhttp://hdl.handle.net/1893/27536
PublisherSpringer Nature
ISSN1939-8018
eISSN1939-8115
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